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HY57V161610D
2 Banks x 512K x 16 Bit Synchronous DRAM
DESCRIPTION
Preliminary
THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16. HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline design is not restricted by a 2N rule.)
FEATURES
* * * * * * Single 3.0V to 3.6V power supplyNote1) All device pins are compatible with LVTTL interface JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM/LDQM Internal two banks operation * * * * Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequence Burst - 1, 2, 4 and 8 for Interleave Burst Programmable CAS Latency ; 1, 2, 3 Clocks
ORDERING INFORMATION
Part No.
HY57V161610DTC-5 HY57V161610DTC-55 HY57V161610DTC-6 HY57V161610DTC-7 HY57V161610DTC-8 HY57V161610DTC-10
Clock Frequency
200MHz 183MHz 166MHz
Organization
Interface
Package
2Banks x 512Kbits x 16 143MHz 125MHz 100MHz
LVTTL
400mil 50pin TSOP II
Note : 1. VDD(min) of HY57V161610DTC-5/55 is 3.15V
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied Rev. 3.3/Mar.99
HY57V161610D
PIN CONFIGURATION
VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50pin TSOP-II 400mil x 825mil 0.8mm pin pitch
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS
PIN DESCRIPTION
PIN CLK Clock PIN NAME DESCRIPTION The system clock input. All other inputs are referenced to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. Command input enable or mask except CLK, CKE and DQM Select either one of banks during both RAS and CAS activity. Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation. Refer function truth table for details DQM control output buffer in read mode and mask input data in write mode Multiplexed data input / output pin Power supply for internal circuit and input buffer Power supply for DQ No connection
CKE CS BA A0 ~ A10
Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection
RAS, CAS, WE
LDQM, UDQM DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ NC
Rev. 3.3/Mar.99
2
HY57V161610D
FUNCTIONAL BLOCK DIAGRAM
1Mx16 Synchronous DRAM
Self Refresh Counter
Refresh Interval Timer
Refresh Counter
512Kx16 Bank 0
Address[0:10] Sense AMP & I/O gates Column Decoder CLK CKE BA(A11) CS RAS CAS WE UDQM LDQM Column Decoder Sense AMP & I/O gates Burst Length Counter Column Active Overflow Column Addr. Latch & Counter Precharge Row Active Address Register DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
512Kx16 Bank 1
Mode Register
Test Mode
I/O Control
Rev. 3.3/Mar.99
3
HY57V161610D
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature*Time TA TSTG VIN, VOUT VDD IOS PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260*10 Rating C C V V mA W C *Sec Unit
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=0C to 70C)
Parameter Power Supply Voltage Input high voltage Input low voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.5 Typ. 3.3 3.0 0 Max 3.6 VDD + 0.3 0.8 Unit V V V Note 1, 2, 3 1, 4 1, 5
Note : 1.All voltages are referenced to VSS = 0V. 2.VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 3.VDD(min) of HY57V161610DTC-5/55 is 3.15V 4.VIH(max) is acceptable 4.6V AC pulse width with 10ns of duration. 5.VIL(min) is acceptable -1.5V AC pulse width with 10ns of duration.
AC OPERATING CONDITION (TA=0C to 70C, VDD=3.0V to 3.6V, VSS=0V)
Parameter AC input high / low level voltage Input timing measurement reference level voltage Input rise / fall time Output timing measurement reference level Output load capacitance for access time measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 30 Unit V V ns V pF 1 Note
Note : 1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF). For details, refer to AC/DC output load circuit. 2. VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns 3. VDD(min) of HY57V161610DTC-5/55 is 3.15V`
Rev. 3.3/Mar.99
4
HY57V161610D
CAPACITANCE (TA=25C, f=1MHz)
Parameter CLK Input capacitance A0 ~ A10, BA CKE, CS, RAS, CAS, WE, UDQM, LDQM DQ0 ~ DQ15 Pin Symbol CI1 CI2 Min 2.5 2.5 Max 4 5 Unit pF pF
Data input / output capacitance
CI/O
4
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Output 30pF
Output
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA=0C to 70C)
Parameter Power Supply Voltage Input leakage current Output leakage current Output high voltage Output low voltage VDD IL IO VOH VOL Symbol Min. 3.0 -1 -1 2.4 Max 3.6 1 1 0.4 Unit V uA uA V V Note 1, 2 3 4 IOH = -4mA IOL =+4mA
Note : 1.VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. 2.VDD(min) of HY57V161610DTC-5/55 is 3.15V 3.VIN = 0 to 3.6V, All other pins are not under test = 0V 4.DOUT is disabled, VOUT=0 to 3.6V
Rev. 3.3/Mar.99
5
HY57V161610D
DC CHARACTERISTICS II (TA=0C to 70C, VDD=3.0V to 3.6V, VSS=0VNote1,2)
Speed Parameter Symbol Test Condition -5 Burst Length=1, One bank active tRAS tRAS(min),tRP tRP(min), IO=0mA CKE VIL(max), tCK = min. CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = min Input signals are changed one time during 2Clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = min CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = min Input signals are changed one time during 2CLKs. All other pins VDD0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable tCK tCK(min), tRAS tRAS(min), IO=0mA All banks active CL=3 CL=2 130 130 130 130 120 110 110 2 -55 -6 -7 -8 -10 Unit Note
Operating Current
IDD1
130
130
120
110
110
110
mA
2
Precharge Standby Current in power down mode
IDD2P IDD2PS
1 mA 1
Precharge Standby Current in non power down mode
IDD2N
20 mA
IDD2NS IDD3P IDD3PS
15 30 mA 30
Active Standby Current in power down mode
Active Standby Current in non power down mode
IDD3N
50 mA
IDD3NS
30 110 110 110 110 110 90 mA 110 mA mA 3
Burst Mode Operating Current
IDD4
Auto Refresh Current Self Refresh Current
IDD5 IDD6
tRRC tRRC(min), All banks active CKE 0.2V
Note : 1.VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. 2.VDD(min) of HY57V161610DTC-5/55 is 3.15V 3.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
Rev. 3.3/Mar.99
6
HY57V161610D
AC CHARACTERISTICS
Parameter
Symbol
(TA=0C to 70C, VDD=3.0V to 3.6V, VSS=0VNote1,2)
-5 Min
Max
-55 Min 5.5 2 2 4.5 5
Max
-6 Min 6 10 2 2 Max
-7 Min 7 10 2.5 2.5 2.5
1.75 Max
-8 Min 8 12 3 3 2.5 2 1 2 1 2 1 2 1 2
Max
-10
Unit Note
Min 10 12 3 3 2.5 2.5 1 2.5 1 2.5 1 2.5 1 2
Max
System clock cycle time
CL=3 CL=2
tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ
5 1.75 1.75
5.5 6 -
6 6 -
6 6 -
ns 7 ns 7 ns ns ns ns ns ns ns ns ns ns 4 4 4 4 4 4 4 4 3 ns ns 3 4 4
Clock high pulse width Clock low pulse width Access time from clock Data-out hold time Data-Input setup time Data-Input hold time Address setup time Address hold time CKE setup time CKE hold time Command setup time Command hold time CLK to data output in low Ztime CLK to data output in high Ztime CL=3 CL=2
1.5 1.5 1 1.5 1 1.5 1 1.5 1 2
2 1.5 1 1.5 1 1.5 1 1.5 1 2
2 1.5 1 1.5 1 1.5 1 1.5 1 2
1
1.75
1
1.75
1
1.75
1 2
tOHZ
2
5
2
5.5
2
6
2
7
2
8
3
10
ns
Note :
1.VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. 2.VDD(min) of HY57V161610DTC-5/55 is 3.15V 3.tCK2 is 8.9ns only when tAC2 is 7.9ns in HY57V161610DTC-6 and HY57V161610DTC-7. 4.Assume tR / tF (input rise and fall time ) is 1ns.
Rev. 3.3/Mar.99
7
HY57V161610D
AC CHARACTERISTICS
(TA=0C to 70C, VDD=3.0V to 3.6V, VSS=0VNote1,2))
-5 Paramter
Symbol
-55
Max
-6
Max
-7 Ma x 100 K Min 70 70 20 45 3 2 1 0 1 4 2 0 2 3 1 1 64 Ma x 100 K Min 70 70 20 45 3 2 1 0 1 4 2 0 2 3 1 1 64
-8 Ma x 100 K Min 70 80 20 45 2 2 1 0 1 3 2 0 2 3 1 1 64
-10 Ma x 100 K Unit Note
Min Operation RAS cycle time Auto Refresh RAS to CAS delay RAS active time RAS precharge time RAS to RAS bank active delay CAS to CAS bank active delay Write command to data-in delay Data-in to precharge command Data-in to active command DQM to data-in Hi-Z DQM to data mask MRS to new command Precharge to data output Hi-Z Power down exit time Self refresh exit time Refresh Time tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ tPDE tSRE tREF 55 15 40 3 2 2 0 2 5 2 0 2 3 1 1 64 tRC 55
Min 55 55
16.5
Min 60 70 18
ns ns ns ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms 3
100 K
38.5
100 K
40 3 2 1 0 1 4 2 0 2 3 1 1 64
3 2 2 0 1 4 2 0 2 3 1 1 64
Note : 1. VDD(min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. 2.VDD(min) of HY57V161610DTC-5/55 is 3.15V 3. A new command can be given tRRC after self refresh exit.
Rev. 3.3/Mar.99
8
HY57V161610D
DEVICE OPERATING OPTION TABLE
HY57V161610DTC-5
CAS Latency 200MHz 183MHz 166MHz 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 8CLKs 7CLKs 7CLKs tRC 11CLKs 10CLKs 10CLKs tRP 3CLKs 3CLKs 3CLKs tAC 4.5ns 5ns 5.5ns tOH 1.5ns 2ns 2ns
HY57V161610DTC-55
CAS Latency 183MHz 166MHz 143MHz 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 7CLKs 7CLKs 7CLKs tRC 10CLKs 10CLKs 10CLKs tRP 3CLKs 3CLKs 3CLKs tAC 5ns 5.5ns 5.5ns tOH 2ns 2ns 2.5ns
HY57V161610DTC-6
CAS Latency 166MHz 143MHz 125MHz 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 7CLKs 7CLKs 6CLKs tRC 10CLKs 10CLKs 9CLKs tRP 3CLKs 3CLKs 3CLKs tAC 5.5ns 5.5ns 6ns tOH 2ns 2.5ns 2.5ns
HY57V161610DTC-7
CAS Latency 143MHz 125MHz 100MHz 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 7CLKs 6CLKs 5CLKs tRC 10CLKs 9CLKs 7CLKs tRP 3CLKs 3CLKs 2CLKs tAC 5.5ns 6ns 7ns tOH 2.5ns 2.5ns 2.5ns
HY57V161610DTC-8
CAS Latency 125MHz 100MHz 83MHz 3CLKs 3CLKs 2CLKs tRCD 3CLKs 2CLKs 2CLKs tRAS 6CLKs 5CLKs 4CLKs tRC 9CLKs 7CLKs 6CLKs tRP 3CLKs 2CLKs 2CLKs tAC 6ns 7ns 7ns tOH 2.5ns 2.5ns 2.5ns
Rev. 3.3/Mar.99
9
HY57V161610D
COMMAND TRUTH TABLE
Command Mode Register Set No Operation Bank Active Read H Read with Auto precharge Write H Write with Auto precharge Precharge All Bank H Precharge selected Bank Burst Stop U/LDQM Auto Refresh Entry Self Refresh 1 Exit L H L H Entry Precharge power down Exit L H L H Entry Clock Suspend Exit L H H L L V X V V X H X H X H X X X H L L H H X H X H X X X H X H X H X X H H H H H L L L H X L H X L L X L L X H H X X H L X V X X X X L L H L X X L X X X V X L H L L X X L H L H X CKEn-1 H H H CKEn X X L X L H L H H H H X Row Address
Column Address
CS L H
RAS L X
CAS L X
WE L X
DQM X X
A0~A9
A10/ AP OP code X
BA
Note
V V
L H L V H H X
Column Address
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. X=Do not care, L=Low, H=High, BA=Bank Address, RA= Row Address, CA=Column Address, Opcode=Operand Code, NOP=No Operation.
Rev. 3.3/Mar.99
11
HY57V161610D
PACKAGE INFORMATION 400mil 50pin Thin Small Outline Package (TC)
1Mx16 Synchronous DRAM UNIT : INCH (mm)
Rev. 3.3/Mar.99
12

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